Method for testing memories with seamless data input/output by interleaving seamless bank commands

ABSTRACT

A method for testing memories has steps of providing seamless data to data input/output pins and providing seamless control commands to each bank at each clock cycle, when the memories receive the seamless data and control commands, and the data input/output pins of memories receive heavy loads status. For SDRAM and DDR-DRAM, control commands and data are seamlessly inputted/outputted at each clock cycle. For RDRAM, control commands are inputted at each “command packet”, whereby data are inputted/outputted at each “data packet” and memories are in the heavy loading status. By providing heavy loading to control pins and data input/output pins of memories, it is easy to detect weakened memories.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for testing memories, and more particularly to a method for testing memories with seamless data input/output by interleaving seamless bank commands so as to detect a weakened memory.

[0003] 2. Description of Related Art

[0004] While dynamic random access memories (DRAM) are manufactured by 0.2 μm process technology or an advanced manufacturing process, a power supply is lower than 3.3 volts, and a clock rate applied is higher than 133 megahertz, and the DRAM performance is then more and more sensitive to noise from external command signals, address signals, input data signals, and intrinsic noise raised from internal circuitry. For such consideration, DRAM designers have to carefully design memory circuits to provide correct data storage/access paths from each memory cell. On the other hand, DRAM manufacturing engineers must carefully control process conditions to guarantee target device/circuit performance. Even so, weakened memory cells still sometimes exist in DRAM chips and weakened data are probably stored. Thus, a challenge to test engineers is to provide a testing program to screen those memories and assist circuit designers to find critical data access paths and to cover device weakness.

[0005] A memory testing program is assembled by a pin condition setting, and a data access pattern. The pin condition setting includes setting of commanding pins, addressing pins and I/O pins. The data access pattern is used to define word-by-word data access paths and its corresponding operational clock rate. The pin condition setting, which includes true table setting and logic high/low voltage setting, is based on DRAM specification reference to data sheet. The data access pattern is, on the other hand, created by specific testing purposes. For instance, a one-dimensional row access pattern for accessing memory cells on a fixed word line (W/L) is applied to check word line continuity; and a one-dimensional column access pattern for accessing memory cells located on the same column is applied to check bit line (BIL) continuity. In the book “Testing Semiconductor Memory” written by A. J. van de Goor, published by John Wiley & Sons, there are traditional two-dimensional checkboards, GALPAT, sliding diagonals, butterfly patterns etc. for providing better fault coverage.

[0006] Usually, programming commands loops are used to carry out the access patterns mentioned above. For example, a memory has four banks (#0˜#3) are shown in FIGS. 5, 6A and 6B, a programmable cycling control command “Bank active—Write or Read—Bank pre-charge” is applied in the single bank (Bank #0), wherein the burst length in FIGS. 5, 6A and 6B is 4. In FIG. 5, while a “write” command is generated, data having four clock lengths are outputted from data input/output terminals (DQ). In FIGS. 6A and 6B, while a “read” command is generated, data in DQ respectively has two and three clock latency. This kind of cycling command is generally used to check basic functions of DRAM chips, however data in DQ are not inputted/outputted seamlessly.

[0007] With reference to FIGS. 7, 8A and 8B, those figures are similar to FIGS. 5, 6A and 6B, with a difference being that a programmable cycling command “Bank active—Write with auto pre-charge or Read with auto pre-charge” is applied in a single bank (Bank #0). This kind of loop is used to check functions of an auto pre-charge.

[0008] With reference to FIGS. 9 to 12, those figures disclose an interleave bank operation. Two banks interleave and four banks interleave operations are shown in FIGS. 9˜10 and FIGS. 11˜12 respectively Such repeated operations are capable to do seamless input/output (I/O) checks for examining I/O performance. Clearly, the operations shown in FIGS. 9 to 12 suffer larger noise due to more compact I/O operations than those shown in FIGS. 5 to 8. Although DQ in FIGS. 9 to 12 are inputted/outputted data seamlessly, control pins of memory still do not receive seamless controlling commands. Even four banks (Bank #0, #1, #2 and #3) receive initial “active” commands, the control pins still retain in a “wait” situation at 14th, 15th, 18th, 19th, 22nd, 23rd, 26th, 27th, clock cycles. Thus the commands shown in FIGS. 9 to 12 are not sufficient to detect weakened memory cells.

[0009] To overcome these shortcomings, the present invention tends to provide a method for testing a memory with seamless data input/output by interleaving seamless bank commands to mitigate and obviate the aforementioned problems.

SUMMARY OF THE INVENTION

[0010] The main object of the present invention is to provide a method for testing memories with seamless data input/output by interleaving seamless bank commands so as to provide seamless data and commands to data input/output pins and control pins of the memory.

[0011] The second object of the present invention is not only to provide a method that suits testing SDRAMs, but also suits testing DDR DRAMs and RDRAMs.

[0012] To achieve the main object, the method in accordance with the present invention comprising steps of:

[0013] transferring data to data input/output (I/O) pins of memories seamlessly;

[0014] inputting control commands to control pins of the memories seamlessly.

[0015] Thus control pins and data input/output pins of memories receive heavy loading due to the seamless control commands, whereby the weakened memories are easily to detect.

[0016] Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIGS. 1A to 1C respectively show a memory testing timing sequence view of first to third embodiments in accordance with the present invention;

[0018]FIGS. 2A to 2D respectively show a memory testing timing sequence view of fourth to seventh embodiments in accordance with the present invention;

[0019]FIGS. 3A to 3C respectively show a DDR-DRAM memory testing timing sequence view in accordance with the present invention;

[0020]FIGS. 4A and 4B respectively show a RDRAM memory testing timing sequence view in accordance with the present invention;

[0021]FIG. 5 is a timing sequence view of a conventional memory testing method showing data writing in a single bank;

[0022]FIGS. 6A and 6B are timing sequence views of a conventional memory testing method showing data reading in a single bank;

[0023]FIG. 7 is a timing sequence view of a conventional memory testing method showing data writing and auto pre-charge in a single bank;

[0024]FIGS. 8A and 8B are timing sequence views of a conventional memory testing method showing data reading and auto pre-charge in a single bank; and

[0025]FIGS. 9, 10A, 10B, 11, 12A and 12B are timing sequence views of a conventional memory testing method showing data reading/writing in multi-banks.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0026] The present invention is a method for testing a memory by providing seamless control commands and data, wherein the memory has at least two banks. By providing seamless control commands and data, the control pins and data input/output pins of the memory receive heavy loading due to the seamless control commands. For SDRAMs and DDR-DRAMs, control commands and data are seamlessly inputted/outputted at each clock cycle. For RDRAMs, control commands are inputted at each “command packet”, whereby data are inputted/outputted at each “data packet” and memories are in heavy loading status. By providing heavy loading to memories, it is easy to detect weakened memories.

[0027] In the following description, “DQ” that appears in figures in accordance with the present invention is used to represent data input/output terminals.

[0028] With reference to FIGS. 1A, 1B and 1C, timing sequence views respectively having burst lengths of 2, 4 and 8 with different cycling control commands are shown.

[0029] With reference to FIG. 1A, after banks #0˜#3 serially receive “active” commands with two clock cycle intervals, control commands “write with auto pre-charge” are inputted to each bank at appropriate intervals. Thus after the bank #3 receives the initial “active” command, control commands (including “active” and “write with auto-pre charge”) are sequentially inputted to the banks #0˜#3 at each clock cycle, whereby data input/output terminals (DQ) have seamless data input/output and remains in a heavy loading status.

[0030] With reference to FIG. 1B, the burst length is 4 and the cycling control commands are programmed as “active, write, write, bank pre-charge”, and the data input/output terminals (DQ) still haveseamless data input/output.

[0031] With reference to FIG. 1C, the burst length is 8. Different types of cycling control commands are provided to each bank. In the bank #0, the control commands are “active, write, write, bank pre-charge, active, bank pre-charge, active, bank precharge”. In the bank #1, the control commands are “active, bank pre-charge, active, write, write, bank pre-charge, active”. In the bank #2, the control commands are “active, bank pre-charge, active, bank pre-charge, active, write, write”. In the bank #3, the control commands is another type that differs from the control commands in banks #0˜#2. Although the control commands types for each bank are different, control pins and data input/output terminal (DQ) still remain in a heavy loading status.

[0032] With reference to FIGS. 2A and 2B, cycling control commands “active, bank with auto pre-charge” are applied to each bank with different latencies(2 and 3). At each clock cycle, one of the banks (bank #0˜#3) still receives a control command, and the data input/output terminals (DQ) has seamless data input/output.

[0033] The present invention not only provides seamless data and control commands to data input/output terminals (DQ) and control pins, but also depends on memory testing requirement to provide a purposeful interrupt or delay to control commands.

[0034] With reference to FIG. 2C, a control command “CKE” is inserted in the cycling control commands, thus the next control command has a one clock cycle delay, whereby the operating accuracy of memories is easily detected.

[0035] With reference to FIG. 2D, a mask control command “DQM” is inserted in the cycling control commands at a purposeful clock cycle, thus data at the purposeful clock cycle are masked.

[0036] The present invention also suits application for DDR-DRAMs and RDRAMs.

[0037] With reference to FIGS. 3A, 3B and 3D, timing sequence views of testing DDR-DRAMs with data writing/reading are respectively shown. The cycling control commands of DDR-DRAMs are similar to the control commands mentioned above. The difference between the data inputting/outputting status of FIGS. 3A, B and D, and the data inputting/outputting status mentioned above is that two data appear at the same clock cycle.

[0038] With reference to FIGS. 4A, 4B and 4C, timing sequence views of testing RDRAMs with data writing/reading are respectively shown, wherein control commands and data are inputted/outputted seamlessly at each “packet” not “clock cycle”.

[0039] Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed. 

What is claimed is:
 1. A method for testing memories with seamless data input/output by interleaving seamless bank commands, comprising the steps of: transferring data to data input/output (I/O) pins of a memory seamlessly; and inputting control commands to control pins of the memory seamlessly.
 2. The method as claimed in claim 1, wherein in the data transferring step, the data are seamlessly inputted to and outputted from the input/output (I/O) pins of the memory.
 3. The method as claimed in claim 1, wherein in the data transferring step, the data are seamlessly inputted to the input/output (I/O) pins of the memory.
 4. The method as claimed in claim 1, wherein in the data transferring step, the data are seamlessly outputted from the input/output (I/O) pins of the memory.
 5. The method as claimed in claim 1, wherein the memory has at least two banks that have the control pins for receiving the control commands.
 6. The method as claimed in claim 1, wherein the memory is a SDRAM, DDR-DRAM or Rambus RDRAM.
 7. The method as claimed in claim 1, wherein in the transferring data step, the data are partly masked to purposely achieve a non-seamless status.
 8. The method as claimed in claim 1, wherein in the inputting control commands step, the control commands are partly delayed.
 9. The method as claimed in claim 1, wherein in the inputting control commands step, the control commands are partly interrupted.
 10. The method as claimed in claim 7, wherein the memory has at least two banks that have the control pins for receiving the control commands.
 11. The method as claimed in claim 8, wherein the memory has at least two banks that have the control pins for receiving the control commands.
 12. The method as claimed in claim 9, wherein the memory has at least two banks that have the control pins for receiving the control commands.
 13. The method as claimed in claim 7, wherein the memory is a SDRAM, DDR-DRAM or Rambus RDRAM.
 14. The method as claimed in claim 8, wherein the memory is a SDRAM, DDR-DRAM or Rambus RDRAM.
 15. The method as claimed in claim 9, wherein the memory is a SDRAM, DDR-DRAM or Rambus RDRAM. 